Traditional mux scan is based on edge-clock, and thus requires correct scan and data timing operation to meet hold-time conditions at the input to the L1 latch (FIGS. 1a and 1b). These requirements create a burden on the chip design cycle, in that the chip designer must ensure that all signals in the scan chain (plurality of latch pairs) and data path arrive at each L1 after the edge clock arrives at L1. If, for example, the scan or data (launched by an L2 using a clock edge) arrives at the latch prior to the same active edge of the clock, the latch will capture the incorrect data when it captures the next cycle value.
Additionally, chip testing occurs at a very wide range of operating conditions, e.g., very low and very high voltage, very low and very high temperature, and thus for the chip to be testable all hold time conditions must be met at all operating points. This includes both scan operation (SE=1) as well as data capture operation (SE=0). Also, it is important for latches to be testable using a number of methods for maximum flexibility.
More specifically, FIG. 1a is a mux scan latch which is known to suffer from hold time exposures. FIG. 1b provides master slave behavior; however, this design does not provide edge-triggered behavior within the latch. Instead, the design of FIG. 1b requires two clocks which reduces maximum frequency under which the network can operate, and increases clock wire power consumption and noise risk. In the design of FIG. 1b, the latch does not provide edge triggered behavior and requires external circuitry to achieve the edge triggered behavior. Specifically, the design of FIG. 1b must include an external phase splitter to allow control over L1 (C) and L2 (B) clocks, in both the positive and negative phase paths.